UVM: Command Line Processors for Debugging

14 Mar Command Line Processors for Debugging

Posted at 19:36h in UVM by IKS 6 Comments

UVM을 이용한 검증을 진행하면서 debugging을 조금 더 수월하게 도와주는 다양한 command line processor에 대해 소개한다.

Debugging Objection

아래 run-time option을 추가하여 objection에 대한 추가적인 정보를 확인할 수 있다.

+UVM_OBJECTION_TRACE

이 option은 Objection Mechanism 페이지에서 설명한 바 있는 objection에 대한 기록과 count 값을 simulation log로 출력한다. Test 중 simulation이 hang 되거나 의도하지 않은 시점에 종료되는 경우 이 option을 이용하여 debugging 할 수 있다.

class my_test extends uvm_test;
  
  // ...

  task run_phase(uvm_phase phase);
    uvm_objection objection;
    super.run_phase(phase);
    phase.raise_objection(this); // raise an objection
    seq.start(env.agent.sequencer);
    phase.drop_objection(this); // drop an objection
  endtask: run_phase
  
endclass: my_test

UVM_INFO @ 0: run [OBJTN_TRC] Object uvm_test_top raised 1 objection(s): count=1  total=1
UVM_INFO @ 0: run [OBJTN_TRC] Object uvm_top added 1 objection(s) to its total (raised from source object uvm_test_top): count=0  total=1
UVM_INFO @ 0: run [OBJTN_TRC] Object uvm_test_top dropped 1 objection(s): count=0  total=0
UVM_INFO @ 0: run [OBJTN_TRC] Object uvm_test_top all_dropped 1 objection(s): count=0  total=0
UVM_INFO @ 0: run [OBJTN_TRC] Object uvm_top subtracted 1 objection(s) from its total (dropped from source object uvm_test_top): count=0  total=0
UVM_INFO @ 0: run [OBJTN_TRC] Object uvm_top subtracted 1 objection(s) from its total (all_dropped from source object uvm_test_top): count=0  total=0

Debugging Configuration Database

아래 run-time option을 추가하여 configuration database에 대한 추가적인 정보를 확인할 수 있다.

+UVM_CONFIG_DB_TRACE

이 option은 uvm_config_db를 이용한 configuration database set, get 등의 결과를 simulation log로 출력한다. 특히, uvm_config_db의 인자가 되는 instance name과 field name은 string이기 때문에 typo가 발생하기 쉬운데, 이를 debugging 하기는 쉽지 않다. 따라서 이 option을 이용하여 set과 get이 원하는 위치의 원하는 instance를 가리키고 있는지 확인하고 set 한 값이 get 한 값과 동일한지 등을 확인할 때 유용하다. Configuration database에 대한 설명은 Configuration Database 페이지를 참고하자.

class my_test extends uvm_test;
  
  // ...

  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    env = my_env::type_id::create("env", this);
    seq = my_sequence::type_id::create("seq");
    // set configuration database
    uvm_config_db#(string)::set(this, "env", "config_str", "hello world");
  endfunction: build_phase
  
endclass: my_test

class my_env extends uvm_env;
  
  // ...

  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    agent = my_agent::type_id::create("agent", this);
    // get configuration database
    if (!uvm_config_db#(string)::get(this, "", "config_str", config_str)) begin
      `uvm_fatal(get_type_name(), "config_str not found");
    end
  endfunction: build_phase
  
endclass: my_env

UVM_INFO @ 0: reporter [CFGDB/SET] Configuration 'uvm_test_top.env.config_str' (type string) set by uvm_test_top = (string) "hello world"
UVM_INFO @ 0: reporter [CFGDB/GET] Configuration 'uvm_test_top.env.config_str' (type string) read by uvm_test_top.env = (string) "hello world"

Debugging Resource Database

아래 run-time option을 추가하여 resource database에 대한 추가적인 정보를 확인할 수 있다.

+UVM_RESOURCE_DB_TRACE

이 option은 uvm_resource_db를 이용한 resource database set, read_by_name 등의 결과를 simulation log로 출력한다. 특별한 이유가 있지 않다면 가급적 uvm_resource_db 대신 uvm_config_db를 사용하는 것을 권장한다. 이에 대한 자세한 이유는 Resource Database 페이지를 참고하자.

class my_test extends uvm_test;
  
  // ...

  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    env = my_env::type_id::create("env", this);
    seq = my_sequence::type_id::create("seq");
    // set resource database
    uvm_resource_db#(string)::set("uvm_test_top.env", "resource_str", "foo bar");
  endfunction: build_phase
  
endclass: my_test

class my_env extends uvm_env;
  
  // ...

  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    agent = my_agent::type_id::create("agent", this);
    // get resource database
    if (!uvm_resource_db#(string)::read_by_name("uvm_test_top.env", "resource_str", resource_str)) begin
      `uvm_fatal(get_type_name(), "resource_str not found");
    end
  endfunction: build_phase
  
endclass: my_env

UVM_INFO @ 0: reporter [RSRCDB/SET] Resource 'uvm_test_top.env.resource_str' (type string) set by  = (string) "foo bar"
UVM_INFO @ 0: reporter [RSRCDB/RDBYNAM] Resource 'uvm_test_top.env.resource_str' (type string) read by  = (string) "foo bar"

Debugging Phase

아래 run-time option을 추가하여 phase에 대한 추가적인 정보를 확인할 수 있다.

+UVM_PHASE_TRACE

이 option은 UVM의 phase에 대한 시작, 종료 등에 대한 결과를 simulation log로 출력한다. 다소 길지만 아래 log를 자세히 보면 UVM 각 phase의 시작, 종료에 대한 정보가 나오는 것을 확인할 수 있다. UVM의 phase jump, domain 등의 advanced 기능이 활용되거나 objection에 의한 simulation hang 등을 debugging 할 때 활용된다. Phase에 대한 자세한 설명은 Phasing Mechanism 페이지를 참고하자.

UVM_INFO @ 0: reporter [PH/TRC/STRT] Phase 'common' (id=974) Starting phase
UVM_INFO @ 0: reporter [PH/TRC/DONE] Phase 'common' (id=974) Completed phase
UVM_INFO @ 0: reporter [PH/TRC/SCHEDULED] Phase 'common.build' (id=1063) Scheduled from phase common
UVM_INFO @ 0: reporter [PH/TRC/STRT] Phase 'common.build' (id=1063) Starting phase
UVM_INFO @ 0: reporter [PH/TRC/DONE] Phase 'common.build' (id=1063) Completed phase
UVM_INFO @ 0: reporter [PH/TRC/SCHEDULED] Phase 'common.connect' (id=1123) Scheduled from phase common.build
UVM_INFO @ 0: reporter [PH/TRC/STRT] Phase 'common.connect' (id=1123) Starting phase
UVM_INFO @ 0: reporter [PH/TRC/DONE] Phase 'common.connect' (id=1123) Completed phase
UVM_INFO @ 0: reporter [PH/TRC/SCHEDULED] Phase 'common.end_of_elaboration' (id=1182) Scheduled from phase common.connect
UVM_INFO @ 0: reporter [PH/TRC/STRT] Phase 'common.end_of_elaboration' (id=1182) Starting phase
UVM_INFO @ 0: reporter [PH/TRC/DONE] Phase 'common.end_of_elaboration' (id=1182) Completed phase
UVM_INFO @ 0: reporter [PH/TRC/SCHEDULED] Phase 'common.start_of_simulation' (id=1241) Scheduled from phase common.end_of_elaboration
UVM_INFO @ 0: reporter [PH/TRC/STRT] Phase 'common.start_of_simulation' (id=1241) Starting phase
UVM_INFO @ 0: reporter [PH/TRC/DONE] Phase 'common.start_of_simulation' (id=1241) Completed phase
UVM_INFO @ 0: reporter [PH/TRC/SCHEDULED] Phase 'common.run' (id=1301) Scheduled from phase common.start_of_simulation
UVM_INFO @ 0: reporter [PH/TRC/STRT] Phase 'common.run' (id=1301) Starting phase
UVM_INFO @ 0: reporter [PH/TRC/SCHEDULED] Phase 'uvm' (id=1557) Scheduled from phase common.start_of_simulation
UVM_INFO @ 0: reporter [PH/TRC/STRT] Phase 'uvm' (id=1557) Starting phase
UVM_INFO @ 0: reporter [PH/TRC/DONE] Phase 'uvm' (id=1557) Completed phase
UVM_INFO @ 0: reporter [PH/TRC/SCHEDULED] Phase 'uvm.uvm_sched' (id=1602) Scheduled from phase uvm
UVM_INFO @ 0: reporter [PH/TRC/STRT] Phase 'uvm.uvm_sched' (id=1602) Starting phase
UVM_INFO @ 0: reporter [PH/TRC/DONE] Phase 'uvm.uvm_sched' (id=1602) Completed phase
UVM_INFO @ 0: reporter [PH/TRC/SCHEDULED] Phase 'uvm.uvm_sched.pre_reset' (id=1692) Scheduled from phase uvm.uvm_sched
UVM_INFO @ 0: reporter [PH/TRC/STRT] Phase 'uvm.uvm_sched.pre_reset' (id=1692) Starting phase
UVM_INFO @ 0: reporter [PH/TRC/SKIP] Phase 'common.run' (id=1301) No objections raised, skipping phase
UVM_INFO @ 0: reporter [PH/TRC/SKIP] Phase 'uvm.uvm_sched.pre_reset' (id=1692) No objections raised, skipping phase
UVM_INFO @ 0: reporter [PH/TRC/DONE] Phase 'uvm.uvm_sched.pre_reset' (id=1692) Completed phase
UVM_INFO @ 0: reporter [PH/TRC/SCHEDULED] Phase 'uvm.uvm_sched.reset' (id=1751) Scheduled from phase uvm.uvm_sched.pre_reset
UVM_INFO @ 0: reporter [PH/TRC/STRT] Phase 'uvm.uvm_sched.reset' (id=1751) Starting phase
UVM_INFO @ 0: reporter [PH/TRC/SKIP] Phase 'uvm.uvm_sched.reset' (id=1751) No objections raised, skipping phase
UVM_INFO @ 0: reporter [PH/TRC/DONE] Phase 'uvm.uvm_sched.reset' (id=1751) Completed phase
UVM_INFO @ 0: reporter [PH/TRC/SCHEDULED] Phase 'uvm.uvm_sched.post_reset' (id=1810) Scheduled from phase uvm.uvm_sched.reset
UVM_INFO @ 0: reporter [PH/TRC/STRT] Phase 'uvm.uvm_sched.post_reset' (id=1810) Starting phase
UVM_INFO @ 0: reporter [PH/TRC/SKIP] Phase 'uvm.uvm_sched.post_reset' (id=1810) No objections raised, skipping phase
UVM_INFO @ 0: reporter [PH/TRC/DONE] Phase 'uvm.uvm_sched.post_reset' (id=1810) Completed phase
UVM_INFO @ 0: reporter [PH/TRC/SCHEDULED] Phase 'uvm.uvm_sched.pre_configure' (id=1869) Scheduled from phase uvm.uvm_sched.post_reset
UVM_INFO @ 0: reporter [PH/TRC/STRT] Phase 'uvm.uvm_sched.pre_configure' (id=1869) Starting phase
UVM_INFO @ 0: reporter [PH/TRC/SKIP] Phase 'uvm.uvm_sched.pre_configure' (id=1869) No objections raised, skipping phase
UVM_INFO @ 0: reporter [PH/TRC/DONE] Phase 'uvm.uvm_sched.pre_configure' (id=1869) Completed phase
UVM_INFO @ 0: reporter [PH/TRC/SCHEDULED] Phase 'uvm.uvm_sched.configure' (id=1928) Scheduled from phase uvm.uvm_sched.pre_configure
UVM_INFO @ 0: reporter [PH/TRC/STRT] Phase 'uvm.uvm_sched.configure' (id=1928) Starting phase
UVM_INFO @ 0: reporter [PH/TRC/SKIP] Phase 'uvm.uvm_sched.configure' (id=1928) No objections raised, skipping phase
UVM_INFO @ 0: reporter [PH/TRC/DONE] Phase 'uvm.uvm_sched.configure' (id=1928) Completed phase
UVM_INFO @ 0: reporter [PH/TRC/SCHEDULED] Phase 'uvm.uvm_sched.post_configure' (id=1987) Scheduled from phase uvm.uvm_sched.configure
UVM_INFO @ 0: reporter [PH/TRC/STRT] Phase 'uvm.uvm_sched.post_configure' (id=1987) Starting phase
UVM_INFO @ 0: reporter [PH/TRC/SKIP] Phase 'uvm.uvm_sched.post_configure' (id=1987) No objections raised, skipping phase
UVM_INFO @ 0: reporter [PH/TRC/DONE] Phase 'uvm.uvm_sched.post_configure' (id=1987) Completed phase
UVM_INFO @ 0: reporter [PH/TRC/SCHEDULED] Phase 'uvm.uvm_sched.pre_main' (id=2046) Scheduled from phase uvm.uvm_sched.post_configure
UVM_INFO @ 0: reporter [PH/TRC/STRT] Phase 'uvm.uvm_sched.pre_main' (id=2046) Starting phase
UVM_INFO @ 0: reporter [PH/TRC/SKIP] Phase 'uvm.uvm_sched.pre_main' (id=2046) No objections raised, skipping phase
UVM_INFO @ 0: reporter [PH/TRC/DONE] Phase 'uvm.uvm_sched.pre_main' (id=2046) Completed phase
UVM_INFO @ 0: reporter [PH/TRC/SCHEDULED] Phase 'uvm.uvm_sched.main' (id=2105) Scheduled from phase uvm.uvm_sched.pre_main
UVM_INFO @ 0: reporter [PH/TRC/STRT] Phase 'uvm.uvm_sched.main' (id=2105) Starting phase
UVM_INFO @ 0: reporter [PH/TRC/SKIP] Phase 'uvm.uvm_sched.main' (id=2105) No objections raised, skipping phase
UVM_INFO @ 0: reporter [PH/TRC/DONE] Phase 'uvm.uvm_sched.main' (id=2105) Completed phase
UVM_INFO @ 0: reporter [PH/TRC/SCHEDULED] Phase 'uvm.uvm_sched.post_main' (id=2164) Scheduled from phase uvm.uvm_sched.main
UVM_INFO @ 0: reporter [PH/TRC/STRT] Phase 'uvm.uvm_sched.post_main' (id=2164) Starting phase
UVM_INFO @ 0: reporter [PH/TRC/SKIP] Phase 'uvm.uvm_sched.post_main' (id=2164) No objections raised, skipping phase
UVM_INFO @ 0: reporter [PH/TRC/DONE] Phase 'uvm.uvm_sched.post_main' (id=2164) Completed phase
UVM_INFO @ 0: reporter [PH/TRC/SCHEDULED] Phase 'uvm.uvm_sched.pre_shutdown' (id=2223) Scheduled from phase uvm.uvm_sched.post_main
UVM_INFO @ 0: reporter [PH/TRC/STRT] Phase 'uvm.uvm_sched.pre_shutdown' (id=2223) Starting phase
UVM_INFO @ 0: reporter [PH/TRC/SKIP] Phase 'uvm.uvm_sched.pre_shutdown' (id=2223) No objections raised, skipping phase
UVM_INFO @ 0: reporter [PH/TRC/DONE] Phase 'uvm.uvm_sched.pre_shutdown' (id=2223) Completed phase
UVM_INFO @ 0: reporter [PH/TRC/SCHEDULED] Phase 'uvm.uvm_sched.shutdown' (id=2282) Scheduled from phase uvm.uvm_sched.pre_shutdown
UVM_INFO @ 0: reporter [PH/TRC/STRT] Phase 'uvm.uvm_sched.shutdown' (id=2282) Starting phase
UVM_INFO @ 0: reporter [PH/TRC/SKIP] Phase 'uvm.uvm_sched.shutdown' (id=2282) No objections raised, skipping phase
UVM_INFO @ 0: reporter [PH/TRC/DONE] Phase 'uvm.uvm_sched.shutdown' (id=2282) Completed phase
UVM_INFO @ 0: reporter [PH/TRC/SCHEDULED] Phase 'uvm.uvm_sched.post_shutdown' (id=2341) Scheduled from phase uvm.uvm_sched.shutdown
UVM_INFO @ 0: reporter [PH/TRC/STRT] Phase 'uvm.uvm_sched.post_shutdown' (id=2341) Starting phase
UVM_INFO @ 0: reporter [PH/TRC/SKIP] Phase 'uvm.uvm_sched.post_shutdown' (id=2341) No objections raised, skipping phase
UVM_INFO @ 0: reporter [PH/TRC/DONE] Phase 'common.run' (id=1301) Completed phase
UVM_INFO @ 0: reporter [PH/TRC/SCHEDULED] Phase 'common.extract' (id=1335) Scheduled from phase common.run
UVM_INFO @ 0: reporter [PH/TRC/DONE] Phase 'uvm.uvm_sched.post_shutdown' (id=2341) Completed phase
UVM_INFO @ 0: reporter [PH/TRC/SCHEDULED] Phase 'uvm.uvm_sched_end' (id=1632) Scheduled from phase uvm.uvm_sched.post_shutdown
UVM_INFO @ 0: reporter [PH/TRC/STRT] Phase 'uvm.uvm_sched_end' (id=1632) Starting phase
UVM_INFO @ 0: reporter [PH/TRC/DONE] Phase 'uvm.uvm_sched_end' (id=1632) Completed phase
UVM_INFO @ 0: reporter [PH/TRC/SCHEDULED] Phase 'uvm.uvm_end' (id=1572) Scheduled from phase uvm.uvm_sched_end
UVM_INFO @ 0: reporter [PH/TRC/STRT] Phase 'uvm.uvm_end' (id=1572) Starting phase
UVM_INFO @ 0: reporter [PH/TRC/DONE] Phase 'uvm.uvm_end' (id=1572) Completed phase
UVM_INFO @ 0: reporter [PH/TRC/STRT] Phase 'common.extract' (id=1335) Starting phase
UVM_INFO @ 0: reporter [PH/TRC/DONE] Phase 'common.extract' (id=1335) Completed phase
UVM_INFO @ 0: reporter [PH/TRC/SCHEDULED] Phase 'common.check' (id=1394) Scheduled from phase common.extract
UVM_INFO @ 0: reporter [PH/TRC/STRT] Phase 'common.check' (id=1394) Starting phase
UVM_INFO @ 0: reporter [PH/TRC/DONE] Phase 'common.check' (id=1394) Completed phase
UVM_INFO @ 0: reporter [PH/TRC/SCHEDULED] Phase 'common.report' (id=1453) Scheduled from phase common.check
UVM_INFO @ 0: reporter [PH/TRC/STRT] Phase 'common.report' (id=1453) Starting phase
UVM_INFO @ 0: reporter [PH/TRC/DONE] Phase 'common.report' (id=1453) Completed phase
UVM_INFO @ 0: reporter [PH/TRC/SCHEDULED] Phase 'common.final' (id=1512) Scheduled from phase common.report
UVM_INFO @ 0: reporter [PH/TRC/STRT] Phase 'common.final' (id=1512) Starting phase
UVM_INFO @ 0: reporter [PH/TRC/DONE] Phase 'common.final' (id=1512) Completed phase
UVM_INFO @ 0: reporter [PH/TRC/SCHEDULED] Phase 'common.common_end' (id=1018) Scheduled from phase common.final
UVM_INFO @ 0: reporter [PH/TRC/STRT] Phase 'common.common_end' (id=1018) Starting phase
UVM_INFO @ 0: reporter [PH/TRC/DONE] Phase 'common.common_end' (id=1018) Completed phase

Disabling Files and Lines from the Report

아래 compile-time option을 추가하여 log에서 file 정보 또는 line 정보를 제외할 수 있다.

-define UVM_REPORT_DISABLE_FILE_LINE

이 option은 run-time option이 아니라 compile-option임에 유의하자. Log에서 file 정보와 line 정보를 제외함으로써 더 compact하게 필수적인 정보만 나타낼 수 있도록 하는 option이다. UVM_REPORT_DISABLE_FILE과 UVM_REPORT_DISABLE_LINE 옵션을 통해 file 정보와 line 정보 중 원하는 것만 선택적으로 제외할 수도 있다. UVM에서 해당 macro는 아래와 같이 처리하고 있다. 참고로 본문 내 simulation log는 모두 이 option을 적용하여 생성되었다.

`ifdef UVM_REPORT_DISABLE_FILE_LINE
    `define UVM_REPORT_DISABLE_FILE
    `define UVM_REPORT_DISABLE_LINE
`endif

References

https://verificationacademy.com/verification-methodology-reference/uvm/docs_1.2/html/files/base/uvm_cmdline_processor-svh.html

IKS

Jung Ik Moon
Verification Engineer

iksciting.com

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14 Mar Command Line Processors for Debugging

Debugging Objection

Debugging Configuration Database

Debugging Resource Database

Debugging Phase

Disabling Files and Lines from the Report

References

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